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Updated 7/15/22

SystemVerilog Page

SystemVerilog for Verification

SystemVerilog for Verification - Book Cover This book is an introduction to the testbench features of the SystemVerilog language. It is meant for anyone who knows basic Verilog (1995) and needs to verify a design. It includes over 300 examples! You can order it from Amazon or Springer.

Book description

SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus guidelines explaining why to choose one style over another. The book clearly explains the concepts of Object Oriented Programming, Constrained Random Testing, and Functional Coverage. The book covers the SystemVerilog verification constructs such as classes, program blocks, randomization, and functional coverage. SystemVerilog for Verification also reviews design topics such as interfaces and array types. There are over 300 code examples and detailed explanations. Learn the inner workings of such concepts as polymorphism, callbacks, and factory patterns. In addition, the book includes hundreds of guidelines to make you more productive with the language, and also explanations for common coding mistakes so you can avoid these traps. The book is based on Synopsys courses, seminars, and tutorials that Chris Spear developed for SystemVerilog, Vera, RVM, and OOP. SystemVerilog for Verification focuses on the best practices for verifying your design using the power of the language.

Podcast

On Design Radio podcast with Chris Spear Listen to the podcast from On Design Radio, featuring an interview with me about the book. Click on the triangle at the bottom of the description to listen.



Sneak Peek

Take a peek at the book. Here are the first pages of each chapter, plus the full table of contents, index, list of examples, and figures.

Code Examples

Here are a few of the code examples from the book.
  • arb_if The arbiter example from Chapter 5.
  • uniquearray The unique array example from Chapter 6.
  • atm_virt_if The ATM switch with virtual interfaces, from Chapter 10.
  • multi_virt_if_port The multiple virtual interface example from Chapter 10, which passes an array of virtual interfaces through a port.
  • multi_virt_if_xmr The multiple virtual interface example from Chapter 10, which passes an array of virtual interfaces through a cross-module reference.

Tricks and Techniques

Vera allowed the user to reserve regions of values, but this did not make it into the SystemVerilog language. Download the Region package, rewritten for SystemVerilog.

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