After that, try the Verification Central web site and the book, The Art of Verification With Vera.

The Reference Verification Methodology (RVM) helps you create high-quality, sophisticated testbenches in OpenVera. (Look for VMM for SystemVerilog summer of 2005.) But what if you want to use some RVM features in Verilog? The RVM-VL package lets you use the rvm_log facility to print messages from Verilog. New 3/05 Also available from SolvNet

Do you need to test a design that uses memory buffers and need to allocate random chucks of memory? The memory region package lets you do all this and more. Want to allocate a memory region, but it has to be longword aligned, and overlap an existing block? No problem? New 3/05 Coming soon to the examples shipped with Vera.

Want to learn about Native Testbench? Here is my Boston / San Jose SNUG paper on Native Testbench. It has lots of tips and techniques for using this tool with new and existing testbenches.

Examples are what you want so here is one showing both Vera and Native Testbench on a project. There are two testbenches, one directed and one random. You can compile the Verilog DUT with either testbench or separatly. Download it now

Generate random data with non-linear distribution. Revised 6/2004 This package of routines allows you to create random data with Poisson, Gaussian, exponential, and even a bathtub distribution. Includes a graphing function for associative arrays. Now updated with DirectC calls and the C code to generate these functions outside of Verilog.

Want to use Perl and Vera together? Try out this example. This has a Vera testbench calling Perl code along with a Verilog model (using VCS). This is the first release, so there may be a few glitches, but it works on Linux with VCS 7.x and Vera 6.x

Getting started with Vera Cycle Simulation A short example on getting started with Vera's cycle simulator. Want to try out a Vera feature, but without all the added complexity of wrapping it with HDL? Give this a try! Updated to work with Native Testbench (VCS 7.1.1 or later)

Vera with Verilog An example of running Vera with VCS for Verilog simulation. Use this to experiment with signal timing and hdl_tasks. Updated to work with Native Testbench (VCS 7.1.1 or later)

Real number package for Vera   The OpenVera language doesn't have real numbers, but this package of DirectC routines will allow to do most of what you need: converting between reals, strings, and integers, plus routine for arithmetic, trig, log, and comparison. Allows arbitrarily complex expressions in a Polish notation. Now updated for Native Testbench with VCS 7.1 or later v1.9, September 2004. Shown at Boston SNUG 2004!

Calling Vera tasks from C This is an example of C code calling Vera tasks, including asynchronous callbacks. Works for Vera's cycle simulator, VCS with static linking and VCS with dynamic linking.

Print/messaging class - Obsolete This has been replaced with the far better rvm_log class that ships with Vera and Native Testbench. The Reference Verification Methodology version has better printing, sorting, filtering, plus promotion / demotion. The later is very useful when you inject errors into a design. Is a parity error a verification error or just a warning? Depends on if you are expecting it or not. So don't edit your error messages - just promote / demote them!

Passing arrays between Vera and C This is an example of passing static and dynamic arrays from Vera to C, and back again. Show for Vera's cycle simulator, VCS with static linking and VCS with dynamic linking. May 2003

Functional coverage (single) example v1.2   This is an example of instance-based functional coverage with the coverage group declared in the class. The results of functional coverage feed back into the random stimulus generator to give 100% coverage faster than if there was no feedback. April 2003

Functional coverage (multi) example v1.1   This example runs multiple short jobs to get full coverage. The parallel testcase runs the same job with different seeds and then generates a report to measure total coverage. The serial testcase runs one job with seed=42, writes a coverage database, then runs a second with seed=99 that reads in the database. By using the previous results, it can get to full coverage in fewer cycles than if it started from scratch. April 2003

Vera mode for Emacs. A Vera mode for use with Emacs. Also check $VERA_HOME/examples for support of the newest language additions. Learn Emacs from my examples.

Readmemh for Vera. This routine will load dynamic and associative arrays with hex data. Let's you specify addresses more flexibly than Verilog! Parameterized type with self checking testbench.

Coding Tip What is the difference between default arguments and optional arguments? Default arguments have values in case they are not specified when the routine is called. For example, define the task:
   task foo(integer a=1, integer b=2, integer c=3);
You can then call it with:
   foo(4,5,6); // a=4, b=5, c=6
   foo(7,8);   // a=7, b=8, c=3
   foo(9);     // a=9, b=2, c=3
   foo();      // a=1, b=2, c=3
   foo(*,*,0); // a=1, b=2, c=0

Optional arguments in OpenVera are arguments that can be left out when the routine is called:
   task bar{(integer d=1), integer e=2);

Which can then be called with:
   bar(3, 4); // d=3, e=4
   bar(5);    // d=1, e=5
   bar();     // d=1, e=2

Note that the parenthesis around b and c in the following are redundant:
   task june(integer a=1, (integer b=2, (integer c=3)));
as trailing default arguments are always optional.